Many memory systems including Storage Subsystem Controllers commonly use DRAM chips mounted on small cards known as DIMMs as common memory modules. The DIMM modules can include several DRAM units, as well as buffers, clocking and a memory controller. The DIMMs are interfaced to the host CPU and Memory controllers via a variety of standard interface buses such as DDR, DDR2, DDR3 and FB-DIMM, which specify the addressing, data, clock, power and ground connections. DRAMs are volatile, so when used in systems such as storage subsystems that require non-volatility, additional batteries and battery monitoring and recharging circuitry must be added to DRAMs to make them non-volatile.
Flash memory is a specific type of EEPROM that is erased and programmed in relatively large blocks. NAND flash memory is becoming cheaper than DRAM on a cost per bit basis and is inherently nonvolatile so battery backup is not required. However, NAND flash operation differs from DRAM, for example, in that erase-operations, which are required before new data can be written, can only be performed on entire blocks of data. In this way NAND flash is similar to a disk drive. NAND flash is also typically slower than DRAM, and NAND flash has different and frequently proprietary chip level interfaces. Typical commercially available NAND flash memory chips require multiplexed input/output (I/O) pins for handling data and commands. A NAND flash memory device is typically accessed with bursts of data, for example, 512 bytes of data might be written to or read from the device in one burst. Thus, NAND flash cannot directly replace DRAM or any other devices that allow byte or word level random access.
Another limitation is that flash memory is subject to faster wear-out than DRAM, because it has a limited number of times that it can be erased and rewritten. This limitation can be offset in part by wear-leveling techniques which involve remapping blocks of the flash in order to prevent the erase-write operations from being concentrated in certain blocks.
FB-DIMM is a daisy chain architecture using a high speed serial interface with fully buffered dual inline memory modules. The architecture includes separate unidirectional read and write channels. All memory control for the DRAM devices resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. Commercially available Advanced Memory Buffer (AMB) integrated circuits, for example those made by Intel Corporation, are compliant with the FB-DIMM Architecture and Protocol Specification. The AMB interface is responsible for handling the FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the FB-DIMM channel. Fully Buffered DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM.
There is a need for nonvolatile memory card designs that are sufficiently similar to those using DRAM so that non-volatile memory can be added to existing systems with minimal changes in the system design.